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dual channel synchronous step - down switcher with integrated fet ad vanced datasheet IDTP9122 march 12, 2014 1 ? 2014 integrated device technology, inc . features ? input voltage range: 2.7 v to 5 . 5 v ? two step - down converters with integrated fets ? buck1: 2 a ? buck 2 : 3a ? buck 2 to operate in buck or switch mode ? factory programmable output voltage: 0.8 - 3.4v ? automatic pfm/pwm or forced pwm mode ? switching frequency 2 m h z ? optional programmable sequence mode ? power good and/or power on reset output ? - 40 c to +85 c operating temperature range ? package: qfn 24 - ld 4 x 4 mm x 0. 8 mm applications point of load regulation in a variety of low power applications: ? solid state disk drive (ssd) power management ? low power usb powered applications ? set top box / tv power supply ? portable gaming description IDTP9122 is a full y integrated power management ic designed to provide 2 factory programmable voltage rails from a single 5v or 3.3v input rail with high efficiency and low quiescent currents in sleep mode or no - load condition. the device offers selectable direct buck enable inputs or a factory programmable sequencing with power good and power on reset generation. to support low power standby operation, the IDTP9122 supports a configurable sleep mode. the IDTP9122 is available in a 4 mm x 4 mm, 24 - ld, q fn package and guaranteed to operate over the ambient temperature range - 40c to +85c . simplified application diagram p v i n 2 p g n d 2 l x 2 f b 2 p v i n 1 v r e f ( o p t i o n a l ) v i n s e l d e v s l p i n g p i o 1 5 g p o 1 6 g p i o 1 7 v i n v g n d p g n d 1 f b 1 l x 1 v o u t 1 v o u t 2 i n p u t v o l t a g e g p i o 1 4 p v i n 2 p g n d 2 l x 2 f b 2 p v i n 1 v r e f ( o p t i o n a l ) v i n s e l g p i o 1 5 g p o 1 6 g p i o 1 7 v i n p g n d 1 f b 1 l x 1 v o u t 1 v o u t 2 i n p u t v o l t a g e g p i o 1 4 v g n d i d t p 9 1 2 2 w i t h v i n s e l ( p i n 4 ) i n s w i t c h c o n f i g u r a t i o n f o r v o u t 2 i d t p 9 1 2 2 w i t h v i n s e l ( p i n 4 ) i n b u c k c o n f i g u r a t i o n f o r v o u t 2 g p i 3 d e v s l p i n g p i 3
IDTP9122 advanced datasheet march 12, 2014 2 ? 2014 integrated device technology, inc. ordering guide table 1 C ordering summary part number marking package ambient temp. range shipping carrier quantity p912 2 - 00nbgi p912 2 - 00nbgi qfn - 24 4x4x0.75mm 24 - ld - 40c to +85c tape or canister 490 p912 2 - xxnbgi p912 2 - xxnbgi qfn - 24 4x4x0.75mm 24 - ld - 40c to +85c tape or canister 490 p912 2 - xxnbgi8 p912 2 - xxnbgi qfn - 24 4x4x0.75mm 24 - ld - 40c to +85c tape and reel 4000 additional ordering information: the IDTP9122 will be sampled in - 00 configuration, with all user configurable otp registers at default state (0). once a final customer configuration has been defined, a con figuration specific - xx id will be assigned and used for order and marking. absolute maximum rat ings stresses above the ratings listed below can cause p ermanent damage to the IDTP9122 . these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificati ons is not implied. exposure to absolute maximum rating conditions for extended periods can affec t product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. table 2 C absolute maximum ratings symbol parameter min max unit pvin1, pvin2 to pgnd regulator input voltage - 0.3 6.0 v v in to gnd s upply for device - 0.3 6.0 v lx1, lx2 regulator switch nodes - 0.3 6.0 v fb1, fb2 regulator feedback pins - 0.3 3.6 v all other pins - 0.3 6.0 v t j operating junction temperature 1 25 c t s storage temperature 150 c t solder soldering temperature (10 seconds) 260 c p d power dissipation (t a = 25c) 2.5 w i d t p 9 1 2 2 C x x n b g i 8 t & r o p t i o n : 8 = t & r , b l a n k = n o t e m p e r a t u r e g r a d e : i = - 4 0 c t o + 8 5 c p a c k a g e c o d e d e v i c e i d p m i c c o d e p o w e r p r e f i x c o n f i g u r a t i o n i d
IDTP9122 advanced datasheet march 12, 2014 3 ? 2014 integrated device technology, inc. table 3 - package thermal resistivity symbol description conditions value units ? ja thermal resistance ( qfn - 24) junction to ambient 40 ? c/w jb thermal characterization parameter ( qfn - 24) junction to board 23 ? c/w p d maximum package power dissipation 1 w esd rating (hbm) human body model (all pins except 20, 21) ? 2000v (hbm) human body model (only pins 20, 21) ? 500v (cdm) charged device model (all pins) ? 500v per jedec spec, the qfn - 24 package is rated at msl3. this thermal rating was calculated based on a jedec standard 4 - layer board with dimensions 3in x 4.5in in still air conditions. actual thermal resistance will be affected by pcb size, solder joint quality, pcb layer count, copper thickness, air flow, altitude, and other unlisted variables. for the qfn - 24 package, the 2.8mm x 2.8mm ep is connected to ground plane with a matrix of 3x3 pcb thermal vias plated through from top t o bott om layers. actual thermal resistance will be affected by pcb size, solder joint quality, pcb layer count, copper thickness, air flow, altitude, and oth er unlisted variables. electrical character istics table 4 C general electrical characteristics typical values at 25 c, unless noted. v pvin1 = v pvin2 = vin= 5v. c o(buck1) = 10uf, c o(buck 2 ) = 20f, l1 = l2 = 1.0h. symbol parameter conditions min typ max unit v vin input voltage range 2.7 5.5 v uvlo threshold, vin rising v insel >1v, buck 2 in switch (3.3v) mode 2.95 3 3.05 v uvlo threshold, vin falling 2.65 2.7 2.75 v uvlo threshold, vin rising vinsel=0v, buck 2 in buck (5v) mode 4.35 4.4 4.45 v uvlo threshold, vin falling 3.95 4.0 4.05 v i q(vin) vin quiescent current device in sleep mode <1 a device in active mode, all bucks = off 100 a v il low level input voltage all inputs 0.65 0.85 v v ih high level input voltage all inputs 1.25 1.45 v i pd pull down current gpio14,15,17 , and gpi3 1 a i pu pull up current devslpin @ vin=5v 5 8 1 0 a r pu selectable pull up resistor optional for gp i o14,15,16,17 and gpi3 50 k t sd thermal shutdown 135 c v pg pg detection threshold % of selected output voltage in buck mode, % of v pvin 2 in switch mode 10 % i od max drive output in push - pull configuration, v ol =0.4v , v fbx 1.8v 4 ma in open drain configuration, v ol =0.4v 12 ma v ref reference voltage output voltage v fb (buck1) /2 v c vref output capacitor v ref 0.1 f i vref reference voltage output current 1. 0 ma
IDTP9122 advanced datasheet march 12, 2014 4 ? 2014 integrated device technology, inc. electrical character istics table 5 C buck1 electrical characteristics v o(buck1) = 1.8 v. typical values at 25c, unless noted. v pvin1 = v pvin2 = vin= 5v. c o(buck1) = 10uf, c o(buck 2 ) = 20f, l 1 = l2 = 1.0h. symbol parameter conditions min typ max unit v pvin1 input voltage range 2.7 5.5 v v o(buck1) output voltage range 0.8 3.4 v regulation voltage accuracy - 2 2 % line regulation v pvin1 = 3.0v to 5v 0.01 0.04 %/v load regulation i out1 = 0.2a to 2a, pwm mode 0.5 mv/a offset voltage in pfm mode v o(pfm) = v o(pwm) + v offset pfm mode 15 mv i shdn(buck1) shutdown current gbd 1 a i q(buck1) quiescent current no load, pfm mode 2 5 a i op(buck1) continuous operating dc current t j < 115c 1.8 a i lim(buck1) current limitation 2 2.5 a r (on) high side switch 110 153 m low side switch 56 78 m r dis(buck1) output discharge resistance 500 65 0 9 00 f sw(buck1) switching frequency pwm mode 1.89 2 2.1 mhz t ssr(buck1) soft - start ramp rate 4 8 12 mv/s i fb1 fb1 input bias current 6 8 a c o(buck1) output capacitor 10 f l o(buck1) output inductor 1 h
IDTP9122 advanced datasheet march 12, 2014 5 ? 2014 integrated device technology, inc. electrical characteristics table 6 C buck 2 C electrical characteristics v o(buck 2 ) = 3.3v typical values at 25c, unless noted. v pvin1 = v pvin2 = vin= 5v. c o(buck1) = 10uf, c o(buck 2 ) = 20f, l 1 = l2 = 1.0h. symbol parameter conditions min typ max unit in buck mode (vinsel=low) v pvin 2 input voltage range 2.7 5.5 v v o(buck 2 ) output voltage range 0.8 3.4 v regulation voltage accuracy - 2 2 % line regulation v pvin 2 = 3.6v to 5v 0.01 0.15 %/v load regulation i out 2 = 0.2a to 2.4 a, pwm mode 0.4 0.5 mv/a offset voltage in pfm mode v o(pfm) = v o(pwm) + v offset pfm mode 15 mv i shdn(buck 2 ) shutdown current 1 a i q(buck 2 ) quiescent current no load, pfm mode 2 8 a i op(buck 2 ) continuous operating dc current t j < 115c 2. 3 a i lim(buck 2 ) peak inductor current 2. 6 3 a r (on) high side switch 64 93 m low side switch 45 61 m r dis(buck 2 ) output discharge resistance 5 00 650 9 00 f sw(buck 2 ) switching frequency pwm mode 1.89 2 2.1 mhz t ssr(buck 2 ) soft - start ramp rate 8 12 mv/s i fb 2 fb 2 input bias current 9 11 a c o(buck 2 ) output capacitor 20 f l o(buck 2 ) output inductor 1 h in switch mode (vinsel=high), c o(buck 2 ) = 10f, v pvin 2 = 3.3v v pvin 2 input voltage range 2.7 3.6 v i shdn(buck2 ) shutdown current 1 a i q(buck 2 ) quiescent current no load 10 a i op(buck 2 ) continuous operating dc current t j < 115c 2 . 4 a i lim(buck 2 ) current limitation 2.8 3 a r (on) high side switch 64 93 m r dis(buck 2 ) output discharge resistance 300 800 t ssr(buck 2 ) soft - start ramp rate 16 mv/s c o(buck 2 ) output capacitor 2 f
IDTP9122 advanced datasheet march 12, 2014 6 ? 2014 integrated device technology, inc. pin configuration an d description table 7 C pin functions by pin number # label type description 1 vgnd gnd device ground connection 2 vref a reference output [ vref= vout (buck 1 ) /2 ] 3 gpi3 di general purpose input (see modes of operation , page 7 , master enable pin when configured. ) 4 vinsel di logic input to select function of buck 2 . logic low = buck operation, h igh = switch operation. 5 devslpin di logic input to activate sleep mode . logic l ow = normal on operation, h igh = sleep operation. 6 fb1 a feedback connection for buck 1 7 lx1 a inductor connection for buck 1 8 pgnd1 gnd power ground for buck 1 9 pvin1 pwr power supply input for buck 1 10 vin pwr device supply input 11 v gnd v gnd device ground connection 12 n/c n/c pin must be left floating/open 13 v gnd v gnd device ground connection 14 gpio14 d i o general purpose input / output (see modes of operation , page 7 ) . 15 gpio15 dio general purpose input / output (see modes of operation , page 7 ) . 16 gpo16 do general purpose output (see modes of operation , page 7 ) . 17 gpio17 dio general purpose input / output (see modes of operation , page 7 ) . 18 fb 2 a feedback connection for buck 2 (buck mode) or output (switch mode) 19 pgnd 2 gnd power ground buck 2 20 lx 2 a inductor connection buck 2 (buck mode) or output (switch mode) 21 lx 2 a 22 pvin 2 pwr power supply input for buck 2 23 pvin 2 pwr 24 vin pwr device supply input ep ep gnd exposed pad, connect to heat sink ground plane
IDTP9122 advanced datasheet march 12, 2014 7 ? 2014 integrated device technology, inc. functional descripti on: overview the IDTP9122 support several modes to control the 2 b uck regulators and to generate status information like pg (power good) or por (power on reset). various device features can be configured during production using one time programmable fuse memory (otp) . during evaluation, the options can be evaluated using the IDTP9122 evaluation kit ( IDTP9122 - eval). the IDTP9122 otp memory is organized into four fuse banks with 34 bits each. bank0 and 1 are used for idt i nternal trimming and calibration. bank2 and 3 are used for customer specific device configuration. modes of operation device power states device operates in three basic power states controlled by the devslpin pin and one optional state (standby) when in mode 3 . figure 1 . device power states regulator control options (mode 0..3) the IDTP9122 supports four different control options for the buck regulator. the functionality of gpi3, gpio14,15, 16, and 17, and is dif ferent for each of the options. ( mode[1:0] = otp bank3[1:0]) table 8 C buck control options mode [1:0] d escription gpi3 gpio14 gpio15 gpo16 gpio17 0 ( default ) buck regulators controlled by i ndividual enable pins (en1, en2 ) nc en1 gnd porb en 2 1 do not use - reserved 2 buck regulators controlled by master enable pin (men) w/ sequence men porb pg1 nc pg 2 3 buck regulators controlled by master enable pin (men) w/ sequence and standby mode support men standby pg1 nc pg 2 /porb s l e e p o n d e v s l p i n ( p i n 5 ) = h i g h d e v s l p i n ( p i n 5 ) = l o w n o p o w e r v i n > v u v l o s t a n d b y m o d e 3 o n l y v i n < v u v l o s t a n d b y ( g p i o 1 4 p i n 1 4 ) = l o w s t a n d b y ( g p i o 1 4 p i n 1 4 ) = h i g h
IDTP9122 advanced datasheet march 12, 2014 8 ? 2014 integrated device technology, inc. mode0 C individual buck control with IDTP9122 configured for mode0, both regulators are individually controlled via enx input pin. the porb output can be configured to indicate various power up conditions. mode1 C do not use - reserved mode2 C master enable pin (men) with sequence with IDTP9122 configured for mode 2 , a configurable state machine will ramp up/down both regulators controlled by the men pin . the porb output can be configured to indicate various power up conditions. individual powe r good output pins indicate the regulator output being established. mode3 C master enable pin (men) with sequence and standby mode with IDTP9122 configured for mode3, a configurable state machine will ramp up/ down both regulators controlled by the men pin. the porb output can be configured to indicate various power up conditions. individual power good output pins indicate the regulator output being established. in addition to mode2, mode3 supports the standby mode entered by asserting the sta ndby pin. during standby, buck1 and/or 2 will be turned off without sequencing. the configuration is configurable via otp. pin description devslpin this pin allows the ic to enter and exit sleep mode. sleep mode is the lowest power state of the device and is activated whe n devslpin is logic high . the device will be on normal operation when devslpin is logic low . see figure 2 C device power states . vinsel this pin allows the function of buck 2 to be changed to a switch function. logic low on this pin puts the channel into buck configuration, and a logic high on this pin puts the channel into switch configuration. pvin 1, pvin2 pvinx is each buck con verters respective power supply input. they provide power to the internal mosfets for the switch mode regulator. their operating range is 2.7v to 5.5v, and a 10uf capacitor is be placed as close as possible to each of the respective pins. an second 10u f capacitor should be used with pvin 2 because of the greater current sourcing capability of this channel. because capacitance derates with voltage, a 10 v rated x7r ceramic capacitors be used. x7r is preferred over x5r because the derating with x7r is less. fo r best performance, each of these power supply inputs are to be connected together on a dedi cated circuit board power plane, and that the trace goi ng from these pins to the dedicated power plane be made as short as possible. y5v capacitors are not recommended because of their general low performance with respect to temperature, voltage derating, and higher resistance at high frequencys minimi zing t heir ability to filter out high frequency noise. vin vin is the power supply input for the rest of the integrated circuit. it too has an operating range of 2.7v to 5.5v, and a 2.2uf 10v ra ted x7r capacitor should be placed as close as possible to its pin . vin should also be tied to the same power plane that the pvinx pins are tied to with as short a trace as possible . y5v capacitors are highly not recommended. pgnd1, pgnd2 these are the dedicated ground pins for each of the respective power supplys. t he traces from these pins , to a dedicated ground plane , should be made as short as possible. vgnd
IDTP9122 advanced datasheet march 12, 2014 9 ? 2014 integrated device technology, inc. vgnd is the ground pin for the rest of the integrated circuit. the trace from this pin, to a dedicated ground plane, should be made as short as possible. e p this is the exposed pad on the bottom side of the ic. it needs to be connected to a circuit board ground plane to maximize the heat di ssipation performance of the ic . vref the vref pin is an internal voltage reference of the ic. it t racks the output voltage of buck 1, at half its value. thi s voltage could be used to interface to the negative input of a comparator as in li - ion low battery indicator applications, when the positive input of the comparator is a voltage divided level from the batterys p ositive node. at the moment of low battery indication , the comparators output changes state from high to low, thereby, indicating a low battery state , and in turn, for example, then allows an electronic system to begin power down operations . a 2.2uf 6.3 v rated x7r capacitor is recommended at this pin. fb1, fb2 fb1 and fb2 are the respective feedback pins of the output voltage for each buck converter. it is the control input for programming the output voltage of each buck converter. because of the idtp9 12 2 s output voltage programmability, the classical resistor divider network is no longer needed, thereby saving six resistor components. the granularity of programmability of the outputs for each channel is 25mv all the way from 0.8000v to 3.3375v. duri ng layout, the feedback traces should be kept as short as possible and should never run parallel to the inductors and the inductor trace leading to the inductor switching pin. feedback traces should always cross inductors a nd inductor traces on separate planes and at right angles. lx1, lx2 lx1, lx2 are the switching pins of the respective buck converters. small footprint chip inductors of 1uh in value have been optimized for use with the idtp912 2 , and connect to the switching pings . the inductors should be placed as close as possible to the lx pins themselves. gpio14, gpio15, gpio17 these three pins have multiple function, but in the default state they serve as enable pins for each of the three buck conver ters accordingly: gpio14 e nables buck 1. logic high enables buck 1. logic low disables buck 1. see table 9 for alternate mode function. gpio15 see table 9 for alternate mode function. gpio16 enables buck 2. logic high enables buck 2 . logic low disables buck 2 . see table 9 for alternate mode function. gpi3 this pin serves no function in default configuration, but when in mode 2 or mode 3 configuration, it serves as a master enabl e pin. i.e., this pin alone will enable all bucks by the change in logic state on its pin. logic high enables all the bucks with sequencing of all the bucks, and logic low disables all the bucks with sequencing of all the bucks. see table 9 for details of gpio14, gpio15, gpo16, goi o17 functionality when the gpi3 pin is configured. gpo16 this pin se rves as a power on reset pin or as a buck 2 power good pin depending up whether the device is in mode 0 or mode 2 and m ode 3 respectively. see table 9 for alternate mode function. component selection the idtp912 2 is a high performance dual dc - dc step down convertor that minimizes the solution size demands of miniature portable electronic devices . it supports 2 outputs with currents up to 3a inside a 4mm x 4mm qfn package, and only requires 3 external components per channel (cin, cout, l) . because it is designed to automatically switch to a pulse frequency modulation scheme at light loads, the idtp912 2 is able to maintain high efficiency across the entire load range while providing ultra - fast load transient response. input capacitor a 10uf ceramic capacitor or greater should be placed close to each pvin pin for each channel for bypassing. its voltage rating sho uld be 10v to accommodate any high frequency noise coming from 5v power supply source. the kemet 0805c106k8ractu is ideal based
IDTP9122 advanced datasheet march 12, 2014 10 ? 2014 integrated device technology, inc. up on performance , cost, and size. for the vin pin, a 2.2uf 10v capacitor is sufficient because the vin pin is powering the low power internal circuitry of the ic. output capacitor a 10uf or greater ceramic capacitor should be placed close to each output inductor. increasing the output capacitance will lower output ripple and improve load transient response but could also increase solution size or cost. the voltage rating of the output c apacitor should be 6.3v and the c1206c106k9ractu is recommended, but for more demanding space constrained designs, the samsung cl10b106mq8nrnc is a good alternative. inductor selection the idtp912 2 has been designed for use with a 1.0uh inductor. a larger inductor will produce lower output voltage ripple, but a slightly smaller inductor will produce faster transient response. the best compromise is a 1.0uh inductor. selection of the inductor needs to ensure maximum operating c urrent not just the dc current , and can be rated for a 40c temperature rise . this maximum operating current or p eak current for a buck converter can be calculated using equation 1 ipeak = iout [1 + r/2] eq (1); where r is the inductor current ripple ratio and equal to r = [ vout (1 C vout/vin) ] / [ iout * l * f ] eq (2); where l and f are the inductor and switching frequency. simplifying gives equat ion 3: ipeak = iout + vout [ ( 1 - vout/vin ) / 2lf) ] eq (3). equation 3 shows that the peak inductor current is inversely related to the switching frequency and inductance . in other words, the lower the switching frequency or inductance, the higher the peak current. peak current also increases as in put voltage increases. the size of the inductor depends on the application, and the recommended inductor is the toko 1239as - h - 1r 0 m for best performance, size, and cost .
IDTP9122 advanced datasheet march 12, 2014 11 ? 2014 integrated device technology, inc. otp register mapping ( bank t2 ) the following table lists all configurable otp registers available in the IDTP9122 . bank0 and bank1 are idt internal use only trimming and calibration registers and not listed. the registers can be programmed for evaluation purpose using the IDTP9122 evaluation kit ( IDTP9122 - eval) with the included gui software. the final production configuration will be programmed by idt during final test. trim bits parametric tr im t2[0] buck1 transconductance selection: relevant for all modes 0 : nominal 1 : 3x transconductance t2[1] buck1 bandwidth selection: relevant for all modes 0 : nominal 1 : 2x bandwidth t2[2] buck1 forced pwm mode: relevant for all modes 0 : auto - switching between pwm & pfm modes 1 : forced pwm mode t2[ 5: 3] reserved t2[6] buck 2 transconductance selection: 0 : nominal 1 : 3x transconductance t2[7] buck 2 bandwidth selection: 0 : nominal 1 : 2x bandwidth t2[8] buck2 forced pwm mode: 0 : auto - switching between pwm & pfm modes 1 : forced pwm mode t2[10:9] power - off sequencer delay 1: relevant only when mode[1:0]?00 off sequencer delay 2: relevant only when mode[1:0]?00
IDTP9122 advanced datasheet march 12, 2014 12 ? 2014 integrated device technology, inc. trim bits parametric trim t2[15:13] buck power - off sequence selection: relevant only when mode[1:0]?00 000 : wait ? buck 2 ? buck1 001 : wait ? buck1 ? buck2 010 : buck1 ? wait ? buck2 011 : buck1 ? buck2 ? wait 100 : buck2 ? buck1 ? wait 101 : buck2 ? wait ? buck1 110 : buck1 ? buck2 111 : wait ? buck1 & buck2 t2[18:16] porb output boolean operator selection: pg=power good 000 : reserved 001 : pg1 010 : reserved 011 : pg 2 10 0 : reserved 101 : pg1 & pg 2 110 : reserved 111 : r eserved t2[19] gpi3 internal pull - up enable: 0 : disable (1 ? a pull - down to vgnd) 1 : enable (100k? pull - up to vin) t2[20] unused t2[21] gpio14 internal pull - up enable: 0 : disable (1 ? a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply voltage selected by gpio14_vio) t2[22] gpio14 open - drain output select: relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[23] gpio14 i/o voltage select: for both input buffer and push - pull output driver. 0 : vout 2 (fb 2 ) 1 : vout1 (fb1) t2[24] gpio15 internal pull - up enable: 0 : disable (1 ? a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply v oltage selected by gpio15_vio) t2[25] gpio15 open - drain output select: relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[26] gpio15 i/o voltage select: for both input buffer and push - pull output driver. 0 : vout 2 (fb 2 ) 1 : vout1 (fb1) t2[27] gpo16 internal pull - up enable: 0 : disable 1 : enable (50k? pull - up to supply voltage selected by gpo16_vo)
IDTP9122 advanced datasheet march 12, 2014 13 ? 2014 integrated device technology, inc. t2[28] gpo16 open - drain output select: 0 : push - pull output 1 : open - drain output t2[29] gpo16 output voltage select: for push - pull output driver. 0 : vout2 (fb 2 ) 1 : vout1 (fb1) t2[30] gpio17 internal pull - up enable: 0 : disable (1 ? a pull - down to vgnd when pin configured as input) 1 : enable (50k? pull - up to supply voltage selected by g pio17_vio) t2[31] gpio17 open - drain output select: relevant only when pin configured as output. 0 : push - pull output 1 : open - drain output t2[32] gpio17 i/o voltage select: for both input buffer and push - pull output driver. 0 : vout2 (fb 2 ) 1 : vout1 (fb1) t2[33] vref output disable: 0 : vref = 0.5 x vout1(fb1) 1 : vref output disabled otp register mapping ( bank t3) trim bits parametric trim t3[1:0] device i/o configuration and control: 00 : individual regulator enable via pins 01 : reserved 10 : master enable control with programmable sequencing 11 : master enable control with programmable sequencing + sleep mode support t3[2] tsd & uvlo fault disable: used for device characterization and burn - in only. 0 : fault event shuts down a ll buck regulators (programmed sequence) 1 : fault ignored t3[5:3] buck power - on sequence selection: relevant only when mode[1:0]?00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? buck1 sleep mode support: relevant only when mode[1:0]=11
IDTP9122 advanced datasheet march 12, 2014 14 ? 2014 integrated device technology, inc. t3[7] reserved t3[8] buck 2 sleep mode support: relevant only when mode[1:0]=11 0 : buck 2 not affected by sleep mode 1 : buck 2 supports sleep mode control trim bits parametric trim t3[10:9] power - on sequencer delay 1: relevant only when mode[1:0]?00 00 : 0.5ms 01 : 1ms 10 : 2ms 11 : 4ms t3[12:11] power - on sequencer delay 2: relevant only when mode[1:0]?00 00 : 0.5ms 01 : 1ms 10 : 2ms 11 : 4ms t3[19:13] vout1 000d : 1.800v(vout1) / 3.300v(vout 2 ) 001d : 0.800v 00 2d : 0.825v 003d : 0.850v : : : : 100d : 3.275v 101d : 3.300v 102d : 3.325v 103d : 3.3375v t3[26:20] reserved t3[33:27] vout2
IDTP9122 advanced datasheet march 12, 2014 15 ? 2014 integrated device technology, inc. application information figure 7. minimum component schematic of IDTP9122 . package information please refer to the documents located under http://www.idt.com/package/nbg24 for detailed package outline, recommended footprint, carrier and rohs information. idtp9120 is using the p1 - nbg24 package option (ep size: 2.8mm)
www.idt.com 6024 silver creek valley road san jose, california 95138 tel: 800 - 345 - 7015 disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or spec ifications described herein at any time and at idts sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice . performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt s products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idts products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone usin g an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks u 2014 1 os and designs, are the property of idt or their respective third party owners. ? copyright 2014 . all rights reserved. IDTP9122 advanced datasheet march 12, 2014 16 ? 2014 integrated device technology, inc.

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